1. Field of the Invention
The present invention relates to data cache coherency in a computer system comprising a split-level cache arrangement.
2. Related Art
A modern computer system includes a memory hierarchy that comprises various memory devices of varying sizes and speeds. Such memory devices include, for example, a small but fast cache memory, and a larger but slower primary memory.
Data can be found in either the cache memory or the primary memory. Also, a plurality of devices (such as a central processing unit and input/output devices) access and update the data contained in the cache memory and the primary memory. Thus, at any time, data may be inconsistent or stale in the cache memory and/or in the primary memory.
This is called the cache coherency problem. The cache coherency problem is magnified in multi-processor computer systems where a plurality of processors each includes one or more caches, and coherency is required among all of the caches.
Systems and methods for maintaining cache coherency are well known and are described in many publicly available documents, such as John L. Hennessy and David A. Patterson, Computer Architecture--A Quantitative Approach (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., U.S.A., 1990), which is herein incorporated by reference in its entirety. These conventional systems and methods are sufficient for solving the cache coherency problems that exist in most computer systems.
New computer architectures, however, may spawn new types of cache coherency problems. These cache coherency problems may be difficult to detect, much less analyze and solve. Conventional cache coherency techniques may not be adequate to solve these new cache coherency problems.
Thus, what is required is a system and method for solving cache coherency related problems that exist in a computer system having a split-level cache arrangement.